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A theoretical yield model for assembly process of area array solder interconnect packages with experimental verification

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2 Author(s)
Chunho Kim ; Assembly Technol. Dev., Intel Corp., Chandler, AZ, USA ; D. F. Baldwin

This paper presents a theoretical yield model for area array solder interconnect process. To achieve a successful solder joint, contact between the solder ball and its associated wettable pad area is essential because without contact, the solder ball cannot initiate wetting its associated pad and, finally, is found an open defect. When an area array solder joints are made simultaneously, it may happen that some of the solder joints in a chip cannot make contact with their associated pads because of the variations of design parameters such as solder ball size, pad size and height, substrate warpage, etc. The yield model provides the relationships of the interconnect yield to the statistical variations of the design parameters. A series of experiments were performed with specially designed area array flip-chips and substrates to verify the model, focusing on the effects of the solder ball size variation and the number of solder joints on interconnect yield. The experimental observations agree well with the model prediction.

Published in:

IEEE Transactions on Electronics Packaging Manufacturing  (Volume:28 ,  Issue: 4 )