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Performance improvement of tall triple gate devices with strained SiN layers

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13 Author(s)
Collaert, N. ; Interuniv. Microelectron. Center, Heverlee, Belgium ; De Keersgieter, A. ; Anil, K.G. ; Rooyackers, R.
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In this letter, we investigate the influence of tensile and compressive SiN layers on the device performance of triple-gate devices with 60-nm fin height and fin widths down to 35 nm. It will be shown that even for narrow fin devices, the nMOS performance improvement can be as high as 20% with tensile strained layers. The improvement seen for pMOS is lower, about 10%. Next to that both compressive as well as tensile SiN layers can increase the pMOS on-state current.

Published in:

Electron Device Letters, IEEE  (Volume:26 ,  Issue: 11 )