A methodology for FPGA-based control implementation

When used for digital compensator implementation, field-programmable gate arrays (FPGAs) allow the use of a short sampling period, and of a customized fixed-point hardware definition wherein each coefficient and each state variable may be represented using a different number of bits. A methodology is presented based on the control system L/sub 1/ or l/sub 1/ norms for computing the appropriate number of bits to represent each quantity. The methodology is shown to be effective for designing hardware for both traditional shift-form and delta-form representations of the compensator. The methodology is applied to the implementation of a magnetic bearing control system. In this example, a delta-form realization requires less hardware than a shift-form realization, and provides a closer approximation to the original analog compensator. The results show that the methodology is useful for the comparison of competing digital compensator structures.