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DFE architectures for high-speed backplane applications

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3 Author(s)
Li, M. ; Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada ; Wang, S. ; Kwasniewski, T.

Embedded and look-ahead decision feedback equalisation (DFE) architectures are proposed to overcome the speed bottleneck of DFE design for high-speed backplane applications. DFE design examples simulated in 0.18 μm CMOS technology demonstrate the feasibility of 10Gbit/s operation over a 34-inch FR4 backplane.

Published in:

Electronics Letters  (Volume:41 ,  Issue: 20 )