By Topic

Reduced complexity 1-bit high-order digital delta-sigma modulator for low-voltage fractional-N frequency synthesis applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $33
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
B. Bornoosh ; Dept. of Electr. & Comput. Eng., Univ. of Tehran, Iran ; A. Afzali-Kusha ; R. Dehghani ; M. Mehrara
more authors

A reduced complexity third-order digital delta-sigma modulator for fractional-N frequency synthesis is presented. The high-performance modulator, which consists of two sub-blocks, has a single-bit output making it best for this sort of application. A good shaping of quantisation noise is achieved using a new architecture for a digital third-order delta-sigma modulator. The hardware required for this modulator is considerably less than that in previously reported leading to lower power and area consumption and a higher operating frequency. The field programmable gate array (FPGA) implementation of the whole system shows an SNR of at least 94 dB and an operating input range of 0.7 of the full scale (0.7 FS) with an oversampling ratio of 167. The post-layout simulation of the digital circuit using 0.25 μm CMOS technology predicts a maximum operating frequency of over 60 MHz at a supply voltage of 1.5 V.

Published in:

IEE Proceedings - Circuits, Devices and Systems  (Volume:152 ,  Issue: 5 )