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The authors describe the silicon implementation of a new sample-and-hold circuit topology. Its main feature is the self correction of the offset voltage that is generated mainly by the mismatch on the differential pair at the input and the charge injected by the NMOS switches in the sampling capacitor. The circuit was implemented in a CMOS CYE 0.8 μm n-well process from AMS. The results, initially obtained from simulations, were compared to real laboratory measurements. The comparison indicates that the measurements and the simulated results have a very strong correspondence. The real circuit is capable of reducing the total sample-and-hold output error to just 0.14% at a sampling rate of 250 kHz, so that a system which operates at 250 K samples can be implemented.