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Customizing 16-bit floating point instructions on a NIOS II processor for FPGA image and media processing

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3 Author(s)
D. Etiemble ; LRI, Paris Sud Univ., Orsay, France ; S. Bouaziz ; L. Lacassagne

We have implemented customized SIMD 16-bit floating point instructions on a NIOS II processor. On several image processing and media benchmarks for which the accuracy and dynamic range of this format is sufficient, a speed-up ranging from 1.5 to more than 2 is obtained versus the integer implementation. The hardware overhead remains limited and is compatible with the capacities of today's FPGAs.

Published in:

3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005.

Date of Conference:

22-23 Sept. 2005