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Reconfigurable instruction interface architecture for private-key cryptography on the Altera Nios-II processor

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3 Author(s)
Moore, P. ; Inst. of Electron., Commun. & Inf. Technol., Queen''s Univ., Belfast, UK ; McLoone, M. ; Sezer, S.

This paper documents the development of a generic interface between the Altera Nios-II FPGA based soft-processor and a private key encryption core implementation. An existing AES encryption core was used for evaluation purposes. It was found that there was an overhead, relative to the time taken for the test encryption core, of between 40.0% and 72.7% dependent on the level of setup already taken, and the key length for the specific encryption operation. To the author's knowledge there has been no published non-algorithm specific interface to private-key encryption algorithms for use with 32-bit processors prior to the publication of this paper.

Published in:

Telecommunications, 2005. advanced industrial conference on telecommunications/service assurance with partial and intermittent resources conference/e-learning on telecommunications workshop. aict/sapir/elete 2005. proceedings

Date of Conference:

17-20 July 2005

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