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The efficiency of algorithms on reconfigurable devices can be increased significantly using concepts of pipelining. However, pipelining must not necessarily be limited to introduce temporal parallelism to the execution paths on the reconfigurable device. It also can help to hide the often long reconfiguration time in the case of dynamic run time reconfiguration, i.e., during processing in one area, another one can be reconfigured. This work formulates the stages on run time reconfigurable systems and shows how to derive optimal partitioning of reconfiguration area with respect to the characteristics of the algorithms to be mapped and the characteristics of the execution platform. The goal of the thesis is to develop a comprehensive model for efficient execution of algorithms on run time reconfigurable systems referring to pipeline based run time reconfiguration.