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This paper introduces a toolset to develop FPGA-like reconfigurable logic which is optimized towards a specific application domain. Compared to existing multi-domain architectures, domain-optimized reconfigurable logic carry much lower area costs and, therefore, might drive the deployment of embedded FPGA-like cores in integrated circuits. An architectural template has been developed that enables the definition of components with a virtually unmatched flexibility. The toolset provides fast feedback on the effect of architectural changes upon mapping results. Once satisfactory optimized, the architecture can actually be implemented in a selected CMOS process technology and, besides soft- and hard- cores, patterns for manufacturing test are generated. Special attention is given to the developed graphical architecture editor and place-and-route tool. An example is included to demonstrate the toolset usage and the advantages of the flexible component definitions. Here, the routing network of a simple architecture is optimized for a set of functions from the MCNC benchmark set and the result compares favorable to that obtained by VPR.
Date of Conference: 24-26 Aug. 2005