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Implementation of ranking filters on general purpose and reconfigurable architecture based on high density FPGA devices

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1 Author(s)
D. Milojevic ; Service des Systemes Logiques et Numeriques, Univ. Libre de Bruxelles, Belgium

In this paper we present the implementation of ranking filters on two different computer architectures. First we consider a general purpose computer based on Intel Pentium 4 microprocessor and we show that when SSE2 extension is used the throughput vary from 20 to 200 MB/sec, depending on the neighborhood size and rank value. Secondly, we consider a reconfigurable architecture using hundreds of processing elements running bit-serial algorithms and implemented in a high density FPGA device. The throughput of such system varies from 900 to 2600MB/sec which is 13 to 40 times faster than the considered general purpose architecture.

Published in:

International Conference on Field Programmable Logic and Applications, 2005.

Date of Conference:

24-26 Aug. 2005