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Performance and energy analysis of task-level graph transformation techniques for dynamically reconfigurable architectures

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2 Author(s)
J. Noguera ; InkJet Commercial Div., Hewlett-Packard, Barcelona, Spain ; R. M. Badia

In this paper, we present an analysis of the impact in both performance and energy of several task-level graph transformation techniques to exploit the parallel processing capabilities of run-time partially reconfigurable architectures. The proposed techniques have been applied to an image processing application (i.e., image sharpening), which has been implemented in a real research platform.

Published in:

International Conference on Field Programmable Logic and Applications, 2005.

Date of Conference:

24-26 Aug. 2005