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A high performance hardware architecture for an SAD reuse based hierarchical motion estimation algorithm for H.264 video coding

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3 Author(s)
Sinan Yalcin ; Fac. of Eng. & Natural Sci., Sabanci Univ., Istanbul, Turkey ; Ates, H.F. ; Hamzaoglu, I.

In this paper, we present a high performance and low cost hardware architecture for real-time implementation of an SAD reuse based hierarchical motion estimation algorithm for H.264/MPEG4 Part 10 video coding. This hardware is designed to be used as part of a complete H.264 video coding system for portable applications. The proposed architecture is implemented in Verilog HDL. The Verilog RTL code is verified to work at 68 MHz in a Xilinx Virtex II FPGA. The FPGA implementation can process 27 VGA frames (640 × 480) or 82 CIF frames (352 × 288) per second.

Published in:

Field Programmable Logic and Applications, 2005. International Conference on

Date of Conference:

24-26 Aug. 2005