By Topic

High performance stereo computation architecture

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
J. Diaz ; Dept. of Comput. Archit. & Technol., Granada Univ., Spain ; E. Ros ; S. Mota ; E. M. Ortigosa
more authors

A simple and fast technique for depth estimation, based on phase measurement has been adopted for the implementation of a real-time stereo system with subpixel resolution on a FPGA device. The technique avoids the attendant problem of phase warping. The designed system takes full advantage of the inherent processing parallelism of FPGA devices to achieve a computation speed of 65 Megapixels per second that can be arranged with a customized frame grabber module to process 52 frames per second of 1280 × 960 pixel resolution. The achieved processing speed is higher than existing approaches. This allows the system to extract real-time disparity values for very high resolution images or use several cameras to improve the system accuracy.

Published in:

International Conference on Field Programmable Logic and Applications, 2005.

Date of Conference:

24-26 Aug. 2005