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In this paper, we present two different implementations of a dynamically reconfigurable Bluetooth Baseband Unit (BB_Unit) using Xilinx Virtex-II FPGAs. The design flow started from a non-RTL SystemC model that has been functionally verified against an untimed SystemC golden model developed at Synopsys. This model was progressively refined (using Synopsys tools) until a synthesizable RTL model was obtained. The Xilinx modular design methodology was used to derive the partial and total bitstreams. Two partitions of the BB_Unit were tested: header-payload (P1) and RX-TX (P2). The best results were obtained for the P2 partition on a XC2V250 component. Such a partition requires three sequential time intervals to process a Bluetooth packet: t_rec + 1_ini + t_proc. The reconfigurable area occupied 4 columns and 24 bus-macros requiring a reconfiguration time of t_rec=480 μs, much smaller than the time slot of 625 is specified to either transmit or receive a packet.