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Programmable numerical function generators: architectures and synthesis method

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3 Author(s)
Sasao, T. ; Dept. of CSE, Kyushu Inst. of Technol., Japan ; Nagayama, S. ; Butler, J.T.

This paper presents an architecture and a synthesis method for programmable numerical function generators of trigonometric functions, logarithm functions, square root, reciprocal, etc. Our architecture uses an LUT (look-up table) cascade as the segment index encoder, compactly realizes various numerical functions, and is suitable for automatic synthesis. We have developed a synthesis system that converts MATLAB-like specification into HDL code. We propose and compare three architectures implemented as a FPGA (field-programmable gate array). Experimental results show the efficiency of our architecture and synthesis system.

Published in:

Field Programmable Logic and Applications, 2005. International Conference on

Date of Conference:

24-26 Aug. 2005