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Power and area optimization for multiple restricted multiplication

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3 Author(s)
Nalin Sidahao ; Dept. of Electr. & Electron. Eng., Imperial Coll. London, UK ; Constantinides, G.A. ; Cheung, P.Y.K.

This paper presents a design and optimization technique for the multiple restricted multiplication problem [N. Sidahao, G. A. Constantinides, and F. Y. Cheung (2004)]. This refers to a situation where a single variable is multiplied by several coefficients which, while not constant, are drawn from a finite set of constants that change with time. The approach exploits dedicated registers in FPGA architecture for further time-step based optimization over previous approaches [N. Sidahao, G. A. Constantinides, and F. Y. Cheung. S. S. Demirsoy, A. G. Dempster, and I. Kale (2003)]. It is also combined with an effective technique, based on high-level power modelling, for power optimization. The problem is formulated into an integer linear program for finding solutions to the minimum-costs. The new approach results up to 22% area saving compared to the optimal non-register approach in [N. Sidahao, G. A. Constantinides, and F. Y. Cheung (2004)], and 80% of all results also show 21%-48% power savings.

Published in:

Field Programmable Logic and Applications, 2005. International Conference on

Date of Conference:

24-26 Aug. 2005