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Exploiting pipelining to tolerate wire delays in a programmable-reconfigurable processor

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5 Author(s)
Chi-Wei Wang ; Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA ; Carter, N.P. ; Kujoth, R.B. ; Cook, J.J.
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As fabrication technologies advance, increasing wire delays in semiconductor systems are leading to larger and larger gaps between the clock rates of circuits implemented in reconfigurable logic and those of conventional microprocessors. In this paper, we present a pipelining scheme for the Amalgam programmable-reconfigurable processor that divides long wire delays into multi-cycle operations and supports overlapping of independent computations. On streaming benchmark programs, this pipelining scheme increases the clock rates of Amalgam's reconfigurable clusters by up to 72%, allowing the pipelined Amalgam to maintain a 2.6× performance advantage over a purely-programmable processor in a wide range of fabrication processes.

Published in:

Field Programmable Logic and Applications, 2005. International Conference on

Date of Conference:

24-26 Aug. 2005

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