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Design of a half-toning integrated circuit based on analog quadratic minimization by non linear multistage switched capacitor network

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5 Author(s)

As part of an effort to build a smart sensor, the authors present the design of a neural network performing the minimization of a quadratic distance between the analog acquired picture and a convolution of the resulting halftoned binary picture. It is shown that using a diffusion kernel and switched-capacitor networks results in an effective halftoning circuit, well-suited to a very compact CMOS implementation. It is concluded that this design methodology can be utilized for the implementation of a large class of early or low-level vision problems, expressed as quadratic cost function minimization

Published in:

Circuits and Systems, 1988., IEEE International Symposium on

Date of Conference:

7-9 Jun 1988

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