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The method of power delivery analysis on a network processor and package design is presented. A current profile was developed from the processor design and validated by the measurements. Distributed current sources were used to model the transient current drawn by the silicon. To model the package correctly, distributed circuit elements were used. The sensitivity of the voltage droop to the current stimulus was studied in order to design the appropriate current ramping steps. Two current profiles were studied with measurements to improve the processor design for power integrity.