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40 Gbit/s limiting output buffer in 80 nm CMOS

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5 Author(s)
Sialm, G. ; Electron. Lab., Swiss Fed. Inst. of Technol., Zurich, Switzerland ; Kromer, C. ; Morf, T. ; Ellinger, F.
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A 40 Gbit/s 1V limiting output buffer for an AC-coupled 50 Ω load with a differential output swing of 660 mV and a gain of 18 dB is presented. A power consumption of only 24 mW and a simulated risetime of 11 ps are achieved by means of a systematic buffer optimisation.

Published in:

Electronics Letters  (Volume:41 ,  Issue: 19 )