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Design-for-testability for embedded delay-locked loops

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2 Author(s)
Egan, T. ; Dept. of Electr. Eng., Santa Clara Univ., CA, USA ; Mourad, S.

This paper introduces a new approach to testing a basic analog-only delay-locked loop (DLL) that is embedded in a field-programmable gate array, an application specific integrated circuit, or a system-on-chip (SoC). Part of the DLL circuitry is duplicated and then connected to the DLL in a way that produces a replica of the control voltage. This shadow of the control voltage is used to measure the loop's response to a step in phase. The concept of test construct (TC) gain is introduced as a means of improving detectability. The benefit of the testing approach is demonstrated by injecting defects into the DLL and detecting them through the TC at the observation point.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:13 ,  Issue: 8 )

Date of Publication:

Aug. 2005

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