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AEthereal network on chip: concepts, architectures, and implementations

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3 Author(s)
K. Goossens ; Philips Res. Lab., Eindhoven, Netherlands ; J. Dielissen ; A. Radulescu

The continuous advances in semiconductor technology enable the integration of increasing numbers of IP blocks in a single SoC. Interconnect infrastructures, such as buses, switches, and networks on chips (NoCs), combine the IPs into a working SoC. Moreover, the industry expects platform-based SoC design to evolve to communication-centric design, with NoCs as a central enabling technology. In this article, we introduce the AEthereal NoC. The tenet of the AEthereal NoC is that guaranteed services (GSs) - such as uncorrupted, lossless, ordered data delivery; guaranteed throughput; and bounded latency - are essential for the efficient construction of robust SoCs. To exploit the NoC capacity unused by the GS traffic, we provide best-effort services.

Published in:

IEEE Design & Test of Computers  (Volume:22 ,  Issue: 5 )