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Design, synthesis, and test of networks on chips

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5 Author(s)
Pande, P.P. ; Sch. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA, USA ; Grecu, C. ; Ivanov, A. ; Saleh, R.
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For networks on chips to succeed as the next generation of on-chip interconnect, researchers must solve the major problems involved in designing, implementing, verifying, and testing them. This article surveys the latest NoC architectures, methods, and tools and shows what must happen to make NoCs part of a viable future.

Published in:

Design & Test of Computers, IEEE  (Volume:22 ,  Issue: 5 )

Date of Publication:

Sept.-Oct. 2005

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