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This paper presents an automated system-level co-design tool for hard real-time distributed embedded systems. The tool generates energy-efficient implementation alternatives from a high-level system description. The obtained implementation alternatives span the whole Pareto-optimal front and hence offer the designer enough freedom in choosing a design alternative based on market requirements. Energy-efficient computing is achieved by applying voltage scaling (VS) to exploit slack periods in the system based on a global view of energy profiles of all tasks and their mappings. The co-synthesis process is enhanced in this paper by an extra allocation refinement step to prevent unnecessary energy dissipation and to enhance the efficiency of VS schemes. The time schedule of tasks is also optimized to maximize the energy reduction achieved by apply VS.
Signals, Circuits and Systems, 2005. ISSCS 2005. International Symposium on (Volume:2 )
Date of Conference: 14-15 July 2005