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Architecture level design space exploration and mapping of hardware

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3 Author(s)
Pandey, Sujan ; Inst. of Microelectron. Syst., Darmstadt, Germany ; Glesner, M. ; Muhlhauser, M.

After the partitioning in Hw/Sw co-design, an efficient mapping of hardware components to the target architectures fulfilling both power and delay requirements are still a challenging task for a system designer. In this paper, high level power/delay estimation to map hardware components to the target architectures based on Petri net is proposed, which helps designers to model hardware architecture at high level and estimates power and delay for several design alternatives. This estimation shows how various solutions are distributed over the entire design space and helps to find an optimal solution. In this approach, we first extract parameters such as capacitances and resistances of a gate from the transistor level and form a library of basic components such as adder, multiplier, FIFO etc. of several sizes with their corresponding power/delay information. We model hardware architecture in Petri net by taking necessary components from the library and estimate power/delay for several design alternatives. For an experimental purpose, we model FFT hardware architecture and the results clearly demonstrate the utility of our techniques for the mapping of hardware based on power/delay information.

Published in:

Signals, Circuits and Systems, 2005. ISSCS 2005. International Symposium on  (Volume:2 )

Date of Conference:

14-15 July 2005