By Topic

A novel FPGA compliant micropipeline

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Y. Zafar ; Dept. of Electron. Eng., M. A. Jinnah Univ., Islamabad, Pakistan ; M. M. Ahmed

In this paper, it has been demonstrated that the concept of micropipeline which is native to full custom design can be imported to a traditionally synchronous environment of field-programmable gate arrays (FPGAs) by introducing delay pads which are implemented with a special technology-independent circuit called single-inverter ring oscillator. The delay pad can be customized with the help of a dividing counter to suit the requirements of various stages of the micropipeline. To implement FPGA compliant micropipeline unbundled data strategy has been adopted by incorporating special event controlled registers as opposed to traditional bundled data approach of micropipeline. A 5-stage reconfigurable micropipeline based load-store machine has been developed to demonstrate the validity of the proposed idea. Furthermore, it has been shown that a particular micropipeline stage functioning at its own pace goes into the sleep mode whenever the following stage is not ready to accept the data hence reducing the overall power consumption of the system.

Published in:

IEEE Transactions on Circuits and Systems II: Express Briefs  (Volume:52 ,  Issue: 9 )