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A multiple integration method is reported that greatly improves the signal-to-noise ratio (SNR) for applications with a high-resolution infrared (IR) focal plane array. The signal from each pixel is repeatedly sampled into an integration capacitor and then output and summed into an outside memory that continues for n read cycles during each period of a frame. This method increases the effective capacity of the charge integration and improves sensitivity. Because a low-noise function block and high-speed operation of the readout circuit is required, a new concept is proposed that enables the readout circuit to perform digitization by a voltage skimming method. The readout circuit was fabricated using a 0.6-μm CMOS process for a 64×64 midwavelength IR HgCdTe detector array. The readout circuit effectively increases the charge storage capacity to 2.4×108 electrons and then provides a greatly improved SNR by a factor of approximately 3.