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This paper presents an efficient VLSI architecture of the (248, 216) Reed-Solomon decoder with erasure correction capability for Blu-ray disc (BD). The proposed architecture is designed with four-stage pipelines: the syndrome and erasure location polynomials calculation, the errata location polynomial calculation, the errata evaluation polynomial calculation, and the Chien search and errata value evaluation. Each stage is carefully balanced to maximize the throughput of the pipeline for BD applications. To solve the key equation, the Berlekamp-Massey algorithm is transformed into a symbol-serial structure and the fully utilized VLSI architecture, maintaining the maximum decoding performance, is proposed. Therefore, the proposed architecture maximizes the throughputs requiring less hardware resources. The gate counts for the proposed RS decoder is 74K using the Hynix 0.35 μm standard cell library and the maximum throughput is 700 Mbps at 100 MHz, which is fast enough for 16× BD applications.