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Variations-aware low-power design with voltage scaling

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4 Author(s)
N. Azizi ; Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada ; M. M. Khellah ; V. De ; F. N. Najm

We present a new methodology which takes into consideration the effect of within-die (WID) process variations on a low-voltage parallel system. We show that in the presence of process variations one should use a higher supply voltage than would otherwise be predicted to minimize the power consumption of parallel systems. Previous analyses, which ignored WID process variations, provide a lower nonoptimal supply voltage which can underestimate the energy/operation by 8.2X. We also present a novel technique to limit the effect of temperature variations in a parallel system. As temperatures increases, the scheme reduces the power increase by 43% allowing the system to remain at its optimal supply voltage across different temperatures.

Published in:

Proceedings. 42nd Design Automation Conference, 2005.

Date of Conference:

13-17 June 2005