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Power optimal dual-Vdd buffered tree considering buffer stations and blockages

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2 Author(s)
King Ho Tam ; Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA ; Lei He

This paper presents the first in-depth study on applying dual Vdd buffers to buffer insertion and multi-sink buffered tree construction for power minimization under delay constraint. To tackle the problem of dramatic complexity increment due to simultaneous delay and power consideration and increased buffer choices, we develop a sampling-based sub-solutions (i.e. options) propagation method and a balanced search tree-based data structure for option pruning. We obtain 17× speedup with little loss of optimality compared to the exact option propagation. Moreover, compared to buffer insertion with single Vdd buffers, dual-Vdd buffers reduce power by 23% at the minimum delay specification. In addition, compared to the delay-optimal tree using single Vdd buffers, our power-optimal buffered tree reduces power by 7% and 18% at the minimum delay specification when single Vdd and dual Vdd buffers are used respectively.

Published in:

Design Automation Conference, 2005. Proceedings. 42nd

Date of Conference:

13-17 June 2005