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A 1.5-V 50-MHz pseudodifferential CMOS sample-and-hold circuit with low hold pedestal

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2 Author(s)
Tsung-Sum Lee ; Dept. of Electron. Eng., Nat. Yunlin Univ. of Sci. & Technol., Taiwan ; Chi-Chang Lu

This paper describes the design strategy and implementation of a low-voltage pseudodifferential double-sampled timing-skew-insensitive sample-and-hold (S/H) circuit with low hold pedestal based on the Miller-effect scheme. The S/H circuit employs bootstrapped switches in order to facilitate low voltage operation. The design considerations for each building block are described in detail. The S/H circuit has been designed using a 0.35-μm 2P4M CMOS technology and experimental results are presented. The 1.5-V S/H circuit operates up to a sampling frequency of 50 MHz with less than -54.6 dB of total harmonic distortion for an input sinusoidal amplitude of 0.8 Vpp. In these conditions, a differential hold pedestal of less than 0.8 mV, 1.6 ns acquisition time at 0.8-V step input, and 0.8 Vpp full-scale differential input range are achieved.

Published in:

Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:52 ,  Issue: 9 )

Date of Publication:

Sept. 2005

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