Referenced Items are not available for this document.
A 100 MHz realization of a 2D DCT (discrete cosine transform) in a compiler is presented. An optimal nibble-serial distributed arithmetic architecture is used for an efficient direct implementation of the DCT. The compiler, which is based on BiCMOS gate array technology and functional module generation technology, is used to support a rapid prototyping environment. An 8×8 inverse 2D DCT example in a 0.8 μm BiCMOS gate array is given to illustrate the performance and flexibility of this approach. The design flow and a proposed development system, the Signal Analysis Workstation (SAW), are shown for customized system integrations
Published in:
Acoustics, Speech, and Signal Processing, 1991. ICASSP-91., 1991 International Conference on
Date of Conference: 14-17 Apr 1991
- Page(s):
- 1233 - 1236 vol.2
- Meeting Date :
- 14 May 1991-17 May 1991
- ISSN :
- 1520-6149
- Print ISBN:
- 0-7803-0003-3
- INSPEC Accession Number:
- 4164661
- Conference Location :
- Toronto, Ont.
- Digital Object Identifier :
- 10.1109/ICASSP.1991.150616
- Product Type:
- Conference Publications
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