An efficient architecture of deblocking filter in H.264/AVC for real-time video processing

This paper proposes efficient hardware architecture to accelerate the deblocking filter for H. 264/JVT/AVC. Deblocking filter operations could be fulfilled for real-time with high clock frequency in the previous method, because loading, storing and filtering operations are processed on different cycles. This paper proposes a new architecture that executes loading/storing operations and filtering operations concurrently. The experimental result shows that the proposed architecture can save 38% of the total consuming cycle compared to the conventional method, and the new architecture makes the deblocking filter operation with the possibility of real time