By Topic

Innovating SRAM design for fast process related defect recognition and failure analysis

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Coppens, P. ; Alcatel Microelectronics, Oudenaarde, Belgium ; Vanhorebeek, G. ; De Backer, E. ; Yuan, X.-J.

A special SRAM has been designed as a yield enhancement vehicle in a 0.35 μm CMOS technology. Extra design rules were added to encourage process defects on certain places and discourage them on others. From the failure signature of a memory cell (0 or 1 failure) and its failure extent (single cell, double cell, bitline, wordline, etc.) one can uniquely determine the process related cause of the failure. By this innovating design any process related defect can be linked with high probability to a certain failure signature and its extent which allows to find easily the location of the failure. By simply testing the SRAM the main cause of failure can be found which can help to drive yield improvement. In this work the design philosophy of this SRAM is described, illustrated with some examples of process related defects that proved the usefulness and the strength of the design.

Published in:

Solid-State Device Research Conference, 1999. Proceeding of the 29th European  (Volume:1 )

Date of Conference:

13-15 Sept. 1999