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We explore the structure effect on electrical characteristics of sub-10-nm double-gate metal–oxide–semiconductor field-effect transistors (DG MOSFETs). To quantitatively assess the nanoscale DG MOSFETs' characteristics, the on/off current ratio, subthreshold swing, threshold voltage , and drain-induced barrier-height lowering are numerically calculated for the device with different channel length ( ) and the thickness of silicon film . Based on our two-dimensional density gradient simulation, it is found that, to maintain optimal device characteristics and suppress short channel effects (SCEs) for nanoscale DG MOSFETs, should be simultaneously scaled down with respect to . From a practical fabrication point-of-view, a DG MOSFET with ultrathin will suppress the SCE, but suffers the fabrication process and on-state current issues. Simulation results suggest that may provide a good alternative in eliminating SCEs of double-gate-based nanodevices.