A 8-b 250-MS/S track-and-hold circuit in 0.18-/spl mu/M CMOS

This paper presents a novel design of a high-speed track-and-hold (T/H) circuit, featuring 8-b resolution up to 250 Ms/s and 100 MHz bandwidth. It is designed in a 0.18 /spl mu/m CMOS process with a supply voltage of 1.8 Volt. The implemented input buffer allows a relatively large input range, 1 v-Vpp differential, and low harmonic distortion at the same time. A switched capacitor topology is used or the T/H circuit and amplifier is a folded cascode OTA with regulated cascode. In order to cancel the offset error between the inputs of an operational amplifier (OP-amp), a correlated double sampling (CDS) is used. The switches used are of transmission gate type. The circuit is supposed to work together with an embedded 250-Ms/s 150 mw 8-bit folding and interpolating CMOS ADC 0.18 /spl mu/m. The track-and-hold consumes 7.7 mw.