By Topic

Design rules to avoid tunnel cracking in VLSI interconnects during process flow

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Brillet, H. ; STMicroelectronics, Crolles, France ; Orain, S. ; Fiori, V. ; Dupeux, M.
more authors

A failure analysis based on an energy approach is used to study a two metal level structure in VLSI interconnects. The failure scenario of a channel cracking at the interface low-k /TaNTa is treated for the first level. A finite element FE model has been developed which shows the impact of the layout and the process on the stress level and interface decohesion probability in this structure. In addition, some general design rules are deduced from these calculations to avert crack propagation in interconnects.

Published in:

Thermal, Mechanical and Multi-Physics Simulation and Experiments in Micro-Electronics and Micro-Systems, 2005. EuroSimE 2005. Proceedings of the 6th International Conference on

Date of Conference:

18-20 April 2005