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Mixed body-bias techniques with fixed Vt and Ids generation circuits

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6 Author(s)
Sumita, M. ; Matsushita Electr. Ind. Co. Ltd. (Panasonic), Nagaokakyo, Japan ; Sakiyama, S. ; Kinoshita, M. ; Araki, Y.
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In sub 1 V CMOS VLSIs, the authors proposed a new body bias generation circuits in which Ids and Vt of pMOS/nMOS become always fixed. The mixed body bias techniques result in positive temperature dependence of the delay, 85% reduction of the delay variation, and 75% improvement of power consumption of SRAM on a mobile processor.

Published in:

Integrated Circuit Design and Technology, 2005. ICICDT 2005. 2005 International Conference on

Date of Conference:

9-11 May 2005