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SRAM is likely to remain the largest, leakiest and most process-sensitive circuit block on chip. FinFET, a width-quantized, quasi-planar, double-gate technology, has emerged as the most likely candidate to replace classical technologies around the 45nm node. This paper studies the impact of FinFET design choices on device and SRAM circuit metrics to understand how its unique properties can be suitably harnessed. Width-quantization limits SRAM sizing choices, while quasi-planarity allows increased cell current by increasing fin height. Conversely, the latter property can be exploited to increase Vt and/or decrease Vdd to achieve exponential leakage savings at constant access time. The authors explored both approaches to selecting the right combination of device structure, Vt and Vdd that achieves maximum stability and minimum leakage over the design space. Increasing Vt with fin height and body thickness improves stability, decreases variability and decreases source-drain leakage exponentially. But this necessitates the use of small tox to control short channel effect; this increases gate leakage exponentially. On the other hand, increasing Vt and decreasing Vdd allows the use of larger tox to maintain short-channel effect and control gate leakage; however, this worsens stability.