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In this paper, we have outlined the growing importance of reliability-aware circuit design. Such reliability-aware device design has long been used for radiation-hard applications. Soon, however, such design techniques may become essential for any IC design based on newer transistor geometries of sub-100 nm CMOS technology. In addition to establishing the importance of device-circuit co-design, we also have proposed novel use of statistical design techniques based on transistor sizing and activity rebalancing for design with transistors with significant time-dependent parameter variation.