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Challenges in implementing high-k dielectrics in the 45nm technology node

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8 Author(s)
Lee, B.H. ; SEMATECH, Austin, TX, USA ; Song, S.C. ; Choi, R. ; Wen, H.-C.
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Metal/high-k gate stack technology is urgently required to continue the scaling of CMOS devices at the 45nm node. However, the challenges of simultaneously implementing metal gate and high-k gate dielectrics into the 45nm technology node have not been addressed. This paper reviews recent advanced gate stack technology to illuminate some of the technical challenges in this area.

Published in:

Integrated Circuit Design and Technology, 2005. ICICDT 2005. 2005 International Conference on

Date of Conference:

9-11 May 2005

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