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The design and implementation of double-precision multiplier in a first-generation CELL processor

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7 Author(s)
J. B. Kuang ; Austin Res. Lab., IBM, Austin, TX, USA ; T. C. Buchholtz ; S. M. Dance ; J. D. Warnock
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We present the double precision multiplier for a 90nm PD-SOI first-generation CELL processor. Dynamic booth logic is designed for scalability and with noise, leakage, and pulse width variation tolerance. Static partial product compression is implemented with replicated bits for performance. The design supports fine-grained clock gating domains for active power reduction.

Published in:

2005 International Conference on Integrated Circuit Design and Technology, 2005. ICICDT 2005.

Date of Conference:

9-11 May 2005