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Clock distribution on a dual-core, multi-threaded Itanium® family microprocessor

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4 Author(s)
Doyle, B. ; Intel Corp., Fort Collins, CO, USA ; Mahoney, P. ; Fetzer, E. ; Naffziger, S.

Clock distribution on the microprocessor codenamed Montecito features four distinct segments and topologies each tuned to a specific purpose. A region based active de-skew (RAD) system reduces the process, voltage, and temperature sources of skew across the 21.5 × 27.7mm2 die during normal operation. Clock vernier devices (CVDs) inserted at each local clock buffer allows 70ps of adjustment via scan. The system supports a constantly varying frequency and consumes less than 25W on its 30mm route from PLL to latch.

Published in:

Integrated Circuit Design and Technology, 2005. ICICDT 2005. 2005 International Conference on

Date of Conference:

9-11 May 2005

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