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A high pipeline and low memory design of JPEG2000 encoder

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3 Author(s)
Kuizhi Mei ; Inst. of Artificial Intelligence & Robotics, Xi''an Jiaotong Univ., China ; Nanning Zheng ; Yuehu Liu

A high pipeline JPEG2000 encoder is implemented with low memory, dual buffers to save the wavelet coefficients and pre-rate allocation are used to reduce on-chip RAM. Pipeline and parallel architecture is used in discrete wavelet transform (DWT), bit-plane encoder (BPE) and arithmetic encoder (AE) to enhance coding speed, byte presentation of rate-distortion (RD) slope simplify searching the threshold value to truncate passes in post-coding rate distortion (PCRD) in Tier2. Packet formation, clock distribution and asynchronous interface are also presented. The encoder is verified on FPGA platform, performance is followed: the size of tile is up to 256 × 256 with code block in size of 32 × 32. Input sampling rate is up to 45M samples/s when Tier1 is working at the clock 100 MHz, difference of the PSNR of image compressed by the encoder and JASPER is less than O.5 db at the rate of 0.4 bit per sample (bps). Equivalent gates synthesized are about 109 K and on-chip RAM is 862 Kb.

Published in:

Consumer Electronics, 2005. (ISCE 2005). Proceedings of the Ninth International Symposium on

Date of Conference:

14-16 June 2005