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An industrially effective environment for formal hardware verification

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7 Author(s)
C. -J. H. Seger ; Strategic CAD Labs, Intel Corp., Hillsboro, OR, USA ; R. B. Jones ; J. W. O'Leary ; T. Melham
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The Forte formal verification environment for datapath-dominated hardware is described. Forte has proven to be effective in large-scale industrial trials and combines an efficient linear-time logic model-checking algorithm, namely the symbolic trajectory evaluation (STE), with lightweight theorem proving in higher-order logic. These are tightly integrated in a general-purpose functional programming language, which both allows the system to be easily customized and at the same time serves as a specification language. The design philosophy behind Forte is presented and the elements of the verification methodology that make it effective in practice are also described.

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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:24 ,  Issue: 9 )