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Fault modeling for MOS digital circuits using current limited switch

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3 Author(s)
Ruan, G. ; Waterloo Univ., Ont., Canada ; Vlach, J. ; Barby, J.

A fault model for MOS digital circuits is presented. Only two types of faults, and node-short and line-open, are needed to model hard physical failures occurring in MOS integrated circuits. Complicated failures are modeled as multiple-faults consisting of a number of faults of these two types. The model is isomorphic to realistic MOS circuits and can be used in simulating NMOS, CMOS, CVSL, DSLL, and dynamic MOS circuits. Three examples have been discussed and the results compared with outputs of circuit-level simulators

Published in:

Circuits and Systems, 1988., IEEE International Symposium on

Date of Conference:

7-9 Jun 1988