Referenced Items are not available for this document.
The authors propose a fault simulation model for CMOS VLSI circuits which can handle physical faults as gate-to-drain/source shorts. A relation is established between the inverse voltage of a fault-free inverter and the faulty output voltage of a faulty inverter. This relation is then used to study the propagation of the faulty signal through a successive gate.<
Published in:
Circuits and Systems, 1988., IEEE International Symposium on
Date of Conference: 7-9 June 1988
- Page(s):
- 677 - 680 vol.1
- Meeting Date :
- 07 Jun 1988-09 Jun 1988
- INSPEC Accession Number:
- 3327054
- Conference Location :
- Espoo, Finland
- Digital Object Identifier :
- 10.1109/ISCAS.1988.15016
- Product Type:
- Conference Publications
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