Referenced Items are not available for this document.
A novel differential pulsewidth control loop (PWCL) is proposed, in which a balanced charge pump is employed so that the PWCL does not require a 50% duty cycle reference clock. A test chip is realised in a 0.35 μm CMOS process, and the measured results show that the tuning range for the duty cycle of the input clock is from 27 to 71% at 1 GHz operating frequency.
Published in:
Electronics Letters
(Volume:41
,
Issue:
17
)
Date of Publication: 18 Aug. 2005
- Page(s):
- 960 - 961
- ISSN :
- 0013-5194
- INSPEC Accession Number:
- 8971969
- Digital Object Identifier :
- 10.1049/el:20051882
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 29 August 2005
- Issue Date :
- 18 Aug. 2005
- Sponsored by :
- Institution of Engineering and Technology
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