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Design and implementation of differential pulsewidth control loop for GHz VLSI systems

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1 Author(s)
Tu, S.H.-L. ; Dept. of Electron. Eng., Fu Jen Catholic Univ., Taipei, Taiwan

A novel differential pulsewidth control loop (PWCL) is proposed, in which a balanced charge pump is employed so that the PWCL does not require a 50% duty cycle reference clock. A test chip is realised in a 0.35 μm CMOS process, and the measured results show that the tuning range for the duty cycle of the input clock is from 27 to 71% at 1 GHz operating frequency.

Published in:

Electronics Letters  (Volume:41 ,  Issue: 17 )