Area and power efficient pattern prediction architecture for filter cache access prediction in the instruction memory hierarchy

The pattern prediction algorithm has been shown in past research to provide substantial improvements in energy consumption, without sacrificing performance when used to predict access to the filter cache in the instruction memory hierarchy. Since, the pattern predictor and the filter cache are an overhead to the existing cache architecture, it is imperative that they should together not lower the energy efficiency of the existing architecture. Thus, the extra energy consumed by the predictor should be minimal as compared to the overall energy reduction achieved by the introduction of the filter cache in the instruction memory hierarchy. In this paper, we present the hardware architecture of a low-power, single-cycle pattern predictor, which can be used in conjunction with the filter cache. The predictor has been functionally validated against results from simple scalar simulations on the MediaBench benchmark suite. The predictor is capable of performing single cycle predictions for processor clocks of over 0.5 GHz (in 0.35/spl mu/ process technology) and adds an area overhead of a mere 1500 to 2700 gates to the silicon area depending on the configuration chosen. The predictor is area and power efficient, and does not add any significant overheads to the processor's power and area budget. Thus providing an elegant and attractive solution for inclusion in modern embedded processors.